/*
	Copyright 2017 Benjamin Vedder	benjamin@vedder.se

	This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
    */

//#ifndef HWCONF_DRV8301_H_
//#define HWCONF_DRV8301_H_
#ifndef __DRV8301_H_
#define __DRV8301_H_

#ifdef __cplusplus
extern "C" {
#endif

//#include "datatypes.h"
#include "main.h"
#include "datatypes.h"

#define   DRV8301_SPI_CS_L	HAL_GPIO_WritePin(DRV8301_CS_GPIO_Port,DRV8301_CS_Pin,GPIO_PIN_RESET)
#define   DRV8301_SPI_CS_H	HAL_GPIO_WritePin(DRV8301_CS_GPIO_Port,DRV8301_CS_Pin,GPIO_PIN_SET)

// Functions
void drv8301_init(void);
//void drv8301_set_oc_adj(int val);
//void drv8301_set_oc_mode(drv8301_oc_mode mode);
int drv8301_read_faults(void);
void drv8301_reset_faults(void);
char* drv8301_faults_to_string(int faults);
//unsigned int drv8301_read_reg(int reg);
void drv8301_write_reg(int reg, int data);
int32_t drv8301_read_reg(int32_t reg);
int utils_middle_of_3_int(int a, int b, int c);
void utils_byte_to_binary(int x, char *b);
extern void terminal_write_reg(int argc, const char **argv);
extern void terminal_read_reg(int argc, const char **argv);
extern void drv8301_set_oc_adj(int val);
extern void drv8301_set_oc_mode(drv8301_oc_mode mode);
void drv8301_set_gain(void);

// Defines
#define DRV8301_FAULT_FETLC_OC		(1 << 0)
#define DRV8301_FAULT_FETHC_OC		(1 << 1)
#define DRV8301_FAULT_FETLB_OC		(1 << 2)
#define DRV8301_FAULT_FETHB_OC		(1 << 3)
#define DRV8301_FAULT_FETLA_OC		(1 << 4)
#define DRV8301_FAULT_FETHA_OC		(1 << 5)
#define DRV8301_FAULT_OTW			  (1 << 6)
#define DRV8301_FAULT_OTSD			(1 << 7)
#define DRV8301_FAULT_PVDD_UV		(1 << 8)
#define DRV8301_FAULT_GVDD_UV		(1 << 9)
#define DRV8301_FAULT_FAULT			(1 << 10)
#define DRV8301_FAULT_GVDD_OV		(1 << 11)

//#define PAL_MODE_RESET                  0U

//#define PAL_MODE_UNCONNECTED            1U

//#define PAL_MODE_INPUT                  2U

//#define PAL_MODE_INPUT_PULLUP           3U

//#define PAL_MODE_INPUT_PULLDOWN         4U

//#define PAL_MODE_INPUT_ANALOG           5U

//#define PAL_MODE_OUTPUT_PUSHPULL        6U

//#define PAL_MODE_OUTPUT_OPENDRAIN       7U

//#define PAL_LOW                         0U

//#define PAL_HIGH                        1U

//#define PAL_STM32_OSPEED_HIGHEST        (3U << 3U)

//typedef struct ch_mutex mutex_t;

//typedef enum {
//	DRV8301_OC_LIMIT = 0,
//	DRV8301_OC_LATCH_SHUTDOWN,
//	DRV8301_OC_REPORT_ONLY,
//	DRV8301_OC_DISABLED
//} drv8301_oc_mode;


#ifdef __cplusplus
}
#endif

#endif /* __DRV8301_H_ */
